1. Field of the Invention
The present invention relates to a semiconductor device having a semiconductor chip and a mounting substrate, which are mutually coupled via a bump.
2. Related Art
Typical structure of a conventional semiconductor chip is formed by wire-bonding an electrode provided on the semiconductor chip with a terminal lead disposed in a peripheral of a package and packaging the chip with an encapsulating resin.
Since maximum number of the terminal leads that can be mounted on the substrate is limited under the circumstances of requiring reduced spacing between the terminal leads for increasing number of the terminals in one semiconductor chip in the packaging process for such structure, it is inevitable to increase the dimension of the package for maintaining an appropriate spacing between terminal leads.
To solve such problem, chips including a bonding portion employing solder and bump, such as a type of package called a chip size package (CSP) and the like is proposed.
An exemplary implementation of a planar structure of a conventional CSP is shown in FIG. 9, and a typical cross-sectional structure and a manufacturing process is shown in FIGS. 10A to 10E. FIG. 9 is a plan view of a CSP 80 from the upper surface side, schematically showing solder bumps 54 in phantom.
As shown in FIG. 9 and FIGS. 10A to 10E, under bump metals (UBM) 12, which are disc-shaped hard Ni plated sheets, is provided on an aluminum electrode 50 in the conventional CSP 80.
The UBM 12 is a diffusion barrier film, functioning as inhibiting a diffusion of components of the solder bump 54 in an aluminum electrode 50. Further, a portion of the aluminum electrode 50 is coated with an SiON film 52 and a polyimide film 10. Further, a solder bump 54 is provided on the UBM 12.
Since the CSP such as the CSP 80 and the like is configured that interconnects are formed to extend from the electrode on the semiconductor chip to the solder bumps arranged in a lattice-shaped pattern on the surface of the package so that the formed interconnect does not exceed the width in the two-dimensional dimension of the semiconductor chip, a relatively smaller size of semiconductor package that is closer to the size of the semiconductor chip can be obtained, without any limitation in the arrangement of device electrodes arranged with a narrow interval on the semiconductor chip.
However, a thermal stress is caused by a difference in thermal expansion coefficients of materials of respective components such as the semiconductor chip and the mounting substrate and the like in the CSP having such miniaturized solder-joint, as shown in FIG. 11, strain may be possibly concentrated on the solder-bump junction, which has not higher structural strength.
Further, in a temperature cycling test or the like, a tensile compressive stress radially extending from a central portion of the semiconductor chip toward a circumference portion thereof as illustrated in FIG. 12 is generated between the ball bump and the mounting substrate by the difference in thermal shrinkages of the mounting substrate and the semiconductor chip, the generated stress is repeatedly exerted on the circumference portion of the contacting surface between the ball bump and the UBM.
In this case, in the conventional structure, the stress tends to be concentrated in particular on the circumference portion of the contacting surface between the ball bump and the UBM, when one piece of hard disc-shaped the UBM repeatedly moves, and therefore a crack may be possibly generated in an aluminum electrode provided under the UBM or in the semiconductor chip.
The semiconductor device described in Japanese Patent Laid-Open No. 2000-299,343 is obtained for inhibiting a breakage and/or a peeling-off of an UBM, a metallic electrode or an insulating film caused by such stress. As shown in FIG. 14, a semiconductor device 90 is composed of a copper interconnect pad 22 partially coated with an insulating film 20 and an insulating film 10, an UBM 12 provided in an portion that is not coated with the insulating film 20 covering a side surface of the copper interconnect pad 22 and the insulating film 10 partially covering the top surface of the copper interconnect pad 22, and a solder bump 4 provided on the UBM 12. In the semiconductor device 90, the width of one opening region is represented by “W”.
As shown in FIG. 14, the semiconductor device 90 is designed to mount a solder bump via the UBM 124 by providing a frame of the insulating film 20 on the copper interconnect pad 22 that is a metallic electrode, and the UBM 12 and the copper interconnect pad 22 are configured to mutually contact only within the opening region of the insulating film 20.
In the semiconductor device 90, a contact area of the UBM 12 and the copper interconnect pad 22 is limited by the dimension of the opening of the insulating film 20. The stress exerted onto the UBM 12 is diminished by limiting the contact area.
However, relaxation of the stress by employing the above-described structure is strictly limited.
In order to solve these problems, the present inventors have eagerly continued the investigation, and then eventually obtained the following conclusion. The present inventors have concluded that, since the UBM is a continuous material consisting of integral films, the stress generated in the UBM is transferred through the interior of the UBM to be exerted on the UBM region except the opening region, even if a reduced width of the opening region is presented.
Further, the present inventors have also concluded that, the contact area between the bump and the UBM is not sufficiently smaller since a length of a side of the UBM along the stress direction is larger, even if the stress is exerted to the UBM from any direction, and thus the stress remains in an end of the UBM, even though the UBM is formed to have a corrugated geometry as in the technology described in Japanese Patent Laid-Open No. 2000-299,343, and therefore efficient relaxation of the stress created in the UBM is limited.
Further, although it is required to provide a broader width of the frame of the insulating film in order to reduce the stress transferred to the external of the opening region through the inside of the UBM, the broader width of the frame may possibly cause an increase in the area of the electrode and/or an increase in the contact resistance between the UBM and the metallic electrode. Configurations according to the present invention will be described as follows.